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ABSTRACT
In this project, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 µm, CMOS technology and at 25degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*107 watt, which illustrates an amazing performance. This paper demonstrates the PDP and Power Consumption of the proposed adders, and the comparison results among another six full adders.
CHAPTER ONE
1.0 INTRODUCTION
Adder is one of the most important components of a CPU (central processing unit). Arithmetic logic unit (ALU), floatingpoint unit and address generation like cache or memory access unit use it. In addition, Full adders are important components in other applications such as digital signal processors (DSP) architectures and microprocessors [15]. Arithmetic functions such as ‘addition’, ‘subtraction’, ‘multiplication’ and ‘division’ are some examples, which use ‘adder’ as a main building block. As a result, design of a highperformance fulladder is very useful and important [2, 3, 68]. On the other hand, increasing demand for portable equipments such as cellular phones, personal digital assistant (PDA), and notebook personal computer, arises the need of using area and power efficient VLSI circuits[2, 912]. Lowpower and highspeed adder cells are used in batteryoperation based devices [1315].
1.1 Half adder
The half adder is an example of a simple, functional digital circuit built from two logic gates. A half adder adds two onebit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest halfadder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. Half adders cannot be used compositely, given their incapacity for a carryin bit.
Example half adder logic diagram
1.2 Full adder
A full adder adds binary numbers and accounts for values carried in as well as out. A onebit full adder adds three onebit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in (in theory from a past addition). The fulladder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The circuit produces a twobit output sum typically represented by the signals Cout and S, where .
Schematic symbol for a 1bit full adder with Cin and Cout drawn on sides of block to emphasize their use in a multibit adder
Full adder adds binary numbers and accounts for values carried in as well as out. A onebit full adder adds three onebit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in (in theory from a past addition). The fulladder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The circuit produces a twobit output sum typically represented by the signals Cout and S, where
The onebit full adder's truth table is:
Inputs
Outputs
A
B
Cin
Cout
S
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
Example full adder logic diagram; the AND gates and the OR gate can be replaced with NAND gates for the same results
A full adder can be implemented in many different ways such as with a custom transistorlevel circuit or composed of other gates. One example implementation is with and .
In this implementation, the final OR gate before the carryout output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as .
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. Equivalently, S could be made the threebit XOR of A, B, and Ci, and Cout could be made the threebit majority function of A, B, and Ci.
1.3 MORE COMPLEX ADDERS
1.3.1 RIPPLE CARRY ADDER
4bit adder with logic gates shown
It is possible to create a logical circuit using multiple full adders to add Nbit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.
The layout of a ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 3 (for carry propagation in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays.
1.3.2 CARRYLOOKAHEAD ADDERS
4bit adder with carry lookahead
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carrylookahead adders. They work by creating two signals (P and G) for each bit position, based on if a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a halfadder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carrylookahead architectures are the Manchester carry chain, Brent–Kung adder, and the Kogge–Stone adder.
Some other multibit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pregenerates sum and carry values for either possible carry input to the block.
Other adder designs include the carrysave adder, carryselect adder, conditionalsum adder, carryskip adder, and carrycomplete adder.
1.3.3 LOOKAHEAD CARRY UNIT
A 64bit adder
By combining multiple carry lookahead adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64bit adder that uses four 16bit CLAs with two levels of LCUs.
1.4 COMPRESSORS
We can view a full adder as a 3:2 lossy compressor: it sums three onebit inputs, and returns the result as a single twobit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1+0+1=10 (decimal number '2'). The carryout represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs.
Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carrysave adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda
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